Description: Verification Engineer Fremont, CA BSEE or BSCS, ... and implementing SystemVerilog / UVM test benches for constrained-random verificationDeveloping ... directed and random test casesExperience with automation/scripting (Python, Perl, sed, ...
27 days ago
... using standard and custom test setups. Analyze test data to identify trends ... areas for improvement Prepare detailed test reports and present findings to ... implementation of reliability test procedures Maintain and calibrate test equipment to ensure ...
5 days ago