... Define, document, and implement a UVM verification environment including agents and scoreboards ... checkers, coverage, and other verification collateral - Run tests on RTL ... recommend fixes - Support post-silicon verification activities of the products working ...
28 days ago
... a CAD or AE engineer, supporting Front End Silicon Design tool flows (Synthesis ...
12 days ago
... Define, document, and implement a UVM verification environment including agents and scoreboards ... , checkers, coverage, and other verification collateral Run tests on RTL ... and recommend fixes Support post-silicon verification activities of the products working ...
6 days ago