Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... great: Mandatory UVM/OVM/SystemVerilog/Python/C/C++ Responsibilities: Architect and Create ... mixed-signal interfaces. Develop test plans and coverage metrics from ...
9 days ago
Description: Role: DFT Engineer Location: Santa Clara, CA Interview: ... -on experience with DFT and test flow with commercial EDA tools ... DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic ...
28 days ago