Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... great: Mandatory UVM/OVM/SystemVerilog/Python/C/C++ Responsibilities: Architect and Create ... mixed-signal interfaces. Develop test plans and coverage metrics from ...
13 days ago
Description: Role: Data Engineer Location: Santa Clara, CA (Onsite/ ... using tools such as PowerShell, Python, C#,
5 days ago