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System test engineer jobs in Santa Clara (2 jobs)

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Design Verification Engineer with UVM,OVM, SystemVerilog & Python

  • PDDN Inc
  • Santa Clara
Description: Role: Design Verification Engineer Location: Santa Clara, CA Interview: ... and Create verification environments using System-Verilog and Universal verification methodology ... mixed-signal interfaces. Develop test plans and coverage metrics from ...
9 hours ago

Senior Engineering Technician

  • Accroid Inc
  • Santa Clara
... a testbed for our developers to test software on various NVIDIA hardware ... them. Additionally, collaborate with Infrastructure Engineers, installing and
4 hours ago

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