Description:
RESPONSIBILITIES: Kforce has a client in Austin, TX that is seeking a Senior IC Layout Engineer who will work closely with circuit designers to generate topological layouts of high-performance, cutting-edge semiconductor products. Responsibilities: * Work closely with circuit designers to complete the physical layout and verification of high-performance analog/mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL Layout and PVS Verification tools in FinFET technologies * Use problem s
Apr 3, 2024;
from:
dice.com