FPGA Engineer

Description:

Job Description : RTL partitioning to fit in multiple FPGAs FPGA Build including RTL to Bit-file generation and adding Debug hooks within FPGA such as Signaltap Downloading Bit-file and Running Software on the FPGA Perl, TCL scripting skills; Debugging issues on the FPGA Build emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Evaluate the implemented design in terms of timing closure and resource utilization and scale up the design into ful